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Federal regulations · Through 2026-08-25 · Newer source version available

15 CFR 231.107: Legacy semiconductor.

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Where this section sits in the code
  1. Title 15—Commerce and Foreign Trade
  2. Subtitle B—Regulations Relating to Commerce and Foreign Trade
  3. CHAPTER II—NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY, DEPARTMENT OF COMMERCE
  4. SUBCHAPTER C—CHIPS PROGRAM
  5. PART 231—CLAWBACKS OF CHIPS FUNDING
  6. Subpart A—Definitions

(a) Legacy semiconductor means:

(1) For the purposes of a semiconductor wafer facility:

(i) A silicon wafer measuring 8 inches (or 200 millimeters) or smaller in diameter; or

(ii) A compound wafer measuring 6 inches (or 150 millimeters) or smaller in diameter.

(2) For the purposes of a semiconductor fabrication facility:

(i) A digital or analog logic semiconductor that is of the 28-nanometer generation or older (i.e., has a gate length of 28 nanometers or more for a planar transistor);

(ii) A memory semiconductor with a half-pitch greater than 18 nanometers for Dynamic Random Access Memory (DRAM) or less than 128 layers for Not AND (NAND) flash that does not utilize emerging memory technologies, such as transition metal oxides, phase-change memory, perovskites, or ferromagnetics relevant to advanced memory fabrication; or

(iii) A semiconductor identified by the Secretary in a public notice issued under 15 U.S.C. 4652(a)(6)(A)(ii).

(3) For the purposes of a semiconductor packaging facility, a semiconductor that does not utilize advanced three-dimensional (3D) integration packaging, under paragraph (b)(3) of this section.

(b) Notwithstanding paragraph (a) of this section, the following are not legacy semiconductors:

(1) Semiconductors critical to national security, as defined in § 231.118;

(2) A semiconductor with a post-planar transistor architecture (such as fin-shaped field field-effect transistor (FinFET) or gate all around field-effect transistor); and

(3) A semiconductor utilizing advanced three-dimensional (3D) integration packaging, such as by directly attaching one or more die or wafer, through silicon vias, through mold vias, or other advanced methods.

Collected 2026-08-27T02:24:24Z. Source file · JSON

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